IBM and Siemens announced a research collaboration on 14 October 2026 to develop the design and manufacturing capabilities behind IBM’s nanostack architecture. The work targets vertically stacked transistors and the software needed to prepare future generations for production.
An odds request at 1xbet ghana depends on server processing as well as network delivery, making processor performance one part of the response chain. During busy fixtures, demand can include account checks and incoming updates across many betting markets.
Transistors arranged above one another
Nanostack technology takes a different approach to placing transistors, as they are aligned and arranged so as to maximize the number of transistors that fit in a specific area. According to IBM’s research, they are capable of squeezing nearly 100 billion transistors in as little as 150 square millimetres. Another aspect of the architecture that makes it interesting is that it can work with different materials in the stack of layers. This opens a lot of room for optimizing the work and energy efficiency of the transistor, and the company is working with Siemens on how to prepare the manufacturing process for commercial production.
Earlier experiments made by IBM involved fusing two wafers with a thin layer of dielectric material and demonstrated the operation of a CMOS inverter, which is a circuit that takes a binary input and outputs its opposite value. The results established a basis for further circuit and manufacturing research with industrial partners.
IBM calls the current research generation its 7-angstrom, or 0.7-nanometre, node. As with modern semiconductor naming, that label describes a technology generation rather than the physical width of every feature.
The vertical arrangement brings additional engineering questions. IBM identifies resistance, capacitance and thermal behaviour among the issues designers must consider as devices interact across stacked levels. Those relationships affect how circuits can be laid out and operated.
Design tools for stacked transistor research
IBM contributes semiconductor-device expertise, while Siemens brings electronic design automation, process simulation and manufacturing software. Their shared programme includes virtual models intended to examine performance and fabrication challenges before physical chips are built.
| Research area | Purpose in the collaboration |
| Virtual device models | Examine nanostack behaviour before fabrication |
| Design optimisation | Explore circuit arrangements suited to stacked devices |
| Lithography development | Improve methods for producing the required chip patterns |
Simulation allows researchers to explore alternatives before committing to fabrication. In computational lithography, software models how patterns print and helps refine the mask geometries used to create them.
Live-betting infrastructure handles more than the number displayed beside a selection. Odds updates and suspension signals have different jobs: a market can continue showing a quotation while bet acceptance is disabled. These states require coordinated software processing; settlement messages carry winning, losing or void outcome information.
During a crowded fixture list, many such updates may arrive alongside account requests. Future processors delivering more work per watt could help handle that workload within a data centre’s power budget, while feed delivery and software coordination remain separate factors.
Performance targets for future processors
IBM’s technical projections include approximately 50% higher performance at fixed power, or around 70% lower power at fixed performance, compared with its 2-nanometre node. These are alternative operating comparisons used to describe the architecture’s potential.
The research also includes SRAM scaling. SRAM is fast memory used within chips, and reducing its footprint can leave room for more local storage alongside logic. IBM presents these memory improvements as another part of nanostack’s development.
Account access through 1xbet login depends on credential verification before an authenticated session begins. At peak times, authentication requests may coincide with bet confirmations and users checking balances, creating several kinds of processing demand around the same sporting events.
More efficient server chips could reduce the energy needed to serve those requests. The eventual capacity benefit would depend on the processor built from the technology and the applications running on it.
An early design kit planned for 2027
A separate IBM announcement on 13 October set out plans for an early research process design kit in the first quarter of 2027. A PDK supplies the models and design rules engineers need to explore a particular manufacturing process.
The initial kit is expected to include:
- Example standard-cell libraries for logic functions.
- An example SRAM design for investigating memory integration.
These resources would let prospective collaborators study placement and routing, create early circuit layouts and evaluate density and power-performance characteristics. IBM describes the release as an early research foundation, with further development required before widespread adoption.
The joint programme and the planned PDK address connected parts of that preparation: understanding device behaviour and giving designers tools to investigate usable circuits. Their next milestones concern design readiness and manufacturing methods for subsequent nanostack generations.
